Abstract

To suppress the effect of dark count noise on single photon avalanche diode (SPAD) detector, the mechanism and method of reducing the dark count rate (DCR) of SPAD device by using a polysilicon field plate is studied in this paper. Based on the 0.18-μm standard CMOS process, a polysilicon field plate located between the P+ active region and shallow trench isolation (STI) is deposited to reduce the dark count noise for a scaleable P+/P-well/deep N-well SPAD structure. Test results show that the DCR of SPAD device decreases by an order of magnitude after the deposition of polysilicon field plates, and its dark count performance at high temperature is even better than that of device without polysilicon field plate at room temperature. The TCAD simulation further indicates that the peak electric field in the guard ring region of the SPAD device is introduced into the STI by the field plate, and the overall electric field in the guard ring region is reduced by 25%. Finally, through modeling and calculating the DCR, the polysilicon field plate weakens the electric field of the guard ring region with high trap density, hence the trap-related DCR is significantly reduced. Therefore, the dark count performance of SPAD detector is effectively improved.

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