Abstract
Today’s architectures are moving towards to exploit more and more parallelism. Instruction level parallelism (ILP) is where multiple instructions are executed simultaneously. Superscalar architecture was one of such evolutions. To exploit ILP superscalar processors fetch and execute multiple instructions in parallel thereby reducing the clock cycles per instruction (CPI). ILP can be exploited either statically by the compiler or dynamically by the hardware. In this paper the basic superscalar approach and the improvements made to the superscalar architectures to exploit more parallelism in execution have been discussed.KeywordsSuperscalar architecturesInstruction level parallelismCPI
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