Recent progress in luminescence tuning of Ce(3+) and Eu(2+)-activated phosphors for pc-WLEDs.

Ultrafast solvent dynamics of room-temperature ionic liquids have been investigated by optical heterodyne-detected Raman-induced Kerr-effect spectroscopy (OHD-RIKES) by studying the effects of cation and anion substitution on the low frequency librational modes. The spectra of two series of imidazolium salts are presented. The first series is based on the 1-butyl-3-methylimidazolium salts [bmim]+ containing the anions trifluoromethanesulfate [TfO]−, bis(trifluoromethanesulfonyl)imide [Tf2N]−, and hexafluorophosphate [PF6]−. The second series is based on [Tf2N]− salts containing the three cations 1-butyl-2,3-dimethylimidazolium [bmmim]+, 1-methyl-3-octylimidazolium [omim]+, and [bmim]+. It is found in all five samples that the signal is due to libration of the imidazolium ring at three frequencies around 30, 65, and 100 cm−1 corresponding to three local configurations of the anion with respect to the cation.

Recent development in color tunable phosphors: A review

Nitride phosphors have witnessed themselves the boom period of last ten years. As a new class of spectral conversion materials in solid state lighting, they are steadily replacing sulfides and othosilicates and playing key roles in producing white light-emitting diodes (wLEDs) with high color rendering, tunable color temperatures and high luminous efficiency. The optical quality and reliability of phosphor-converted wLEDs depend exclusively on the performance of phosphors used, so that the performance enhancement of nitride phosphors, which determines their real applicability, must be on the agenda. This article initiates the discussion on the improvement/modification of photoluminescence intensity, emission spectra, quantum efficiency, and thermal quenching/degradation of nitride phosphors. The effects of compositional tailoring (including the doping level, cationic and anionic substitutions), co-doping and post-treatment on the phosphor performance are overviewed. Finally, to make the strategies for the performance enhancement more effective, strengthening the structural analysis is suggested.

Combined data of photoelectron spectra and photoionization efficiency curves in the near threshold ionization region of isolated ion pairs from [emim][Tf(2)N], [emim][Pf(2)N], and [dmpim][Tf(2)N] ionic liquid vapors reveal small shifts in the ionization energies of ion-pair systems due to cation and anion substitutions. Shifts toward higher binding energy following anion substitution are attributed to increased electronegativity of the anion itself, whereas shifts toward lower binding energies following cation substitution are attributed to an increase in the cation-anion distance that causes a lower Coulombic binding potential. The predominant ionization mechanism in the near threshold photon energy region is identified as dissociative ionization, involving the dissociation of the ion pair and the production of intact cations as the positively charged products.

Phosphor conversion generates over 95% of the light source lumens and affects efficacy, spectral tuning and quality of Solid State Lighting (SSL) devices as much as the efficient generation of suitable primary light from the pumping semiconductor chips. In SSL, a large number of applications such as low/mid-power distributed area illumination may not need the highest luminance sources that typically bring along most stringent requirements on materials, for example, as with high-brightness spotlights or automotive headlights. The cumulative efficiency of handling generated photons matters everywhere. Basic properties of phosphors like refractive index and temperature-dependent quantum efficiency, in a series of physical processes and according to conditions surrounding the converter (for example optical scattering and reflection off of various interfaces, transmission and heat conductivity through materials), determine the overall amount of light being extracted and in use. Modifying the light scattering, reflectance and transmission in different conversion media types and adding to it options for reducing the converter temperature has the cumulative effect that allows for optimizing the light generation process. Crucial to the overall efficiency are losses both from light recycled back into the LED, from various reflective surfaces, and weak volume absorption, including self-absorption of the phosphor emission. The influence of these factors will be demonstrated through examples of thermal-optical modeling and actual measurements on specific packaging configurations for a range of forward currents If. For example, advantages gained through controlling the scattering in ceramics versus powder-in-silicone and using thermally conductive materials will be elaborated. The gains can be realized in either efficacy or luminous flux.

Friction drag of bearings is a major energy loss causing parameter in a typical vehicle power train. This paper explains power consumption reduction in an electric vehicle by reducing friction drag of front axle bearings. The design parameters in bearings are modified to minimize friction drag and thus increase overall range of the vehicle. Testing results show that optimization of bearing design can result in significantly lower power consumption hence increasing vehicle efficiency. Testing methodologies are innovated and reinvented to understand the phenomenon. Testing results and calculations establish the claims in reduction of power consumption. The effect of higher energy losses due to rolling resistance are prominent in Electric-Vehicles as compared to IC-Engine cars due to significantly lower power-train losses which overshadow rolling resistance losses in conventional cars.

Implementation of combinational logic circuits in combination with Vedic maths sutra has many advantages over traditional multiplier circuits, such as reduced time delay, less resource utilization, and less power consumption by the selection of the proper FPGA family.Multiplication is one of the important instructions used for performing complex operations in DSP processors.The proposed paper presents the use of Urdhva-Tiryagbhyam Sutra for the square operation.The results of the designed Vedic circuit show that, there is a 17.36% reduction in time delay and an 8.13% reduction in power consumption in Spartan-7 than Artix-7.There is a 33.6% reduced time delay than the Nikhilam sutra, 45.87% reduced delay than the Yavadunam sutra, 87.07%less delay than the Booth multiplier, and 67.83% reduced delay than Booth Wallace multiplier.Thus, implementing the Vedic Sutra for finding the square of a given number causes a reduction in time delay, power consumption and small chip size.

Effects of cation and anion substitution in KVPO4F for K-ion batteries

Experimental and theoretical results of the study of MnFeAsyP1−y (0.15 ≤ y ≤ 0.66) and Mn2−xFexAs0.5P0.5 (0.5 ≤ x ≤ 1.0) systems were analyzed in order to determine the main factors responsible for the mechanism by which antiferromagnetic phase is formed in each of the two systems. It is shown that in the case of cation substitution in the Mn2−xFexAs0.5P0.5 system the main contribution to the mechanism of changing the magnetic ordering phase type is due to a considerable change of electron filling of the magnetically active d-band. As for the MnFeAsyP1−y system with anion substitution, destabilization of the ferromagnetic phase and formation of the antiferromagnetic phase with decreasing As concentration may be due to the changes in the density of electronic states because of a considerable reduction of the unit cell volume.

Synthesis and electrochemical properties of spherical spinel Li 1.05M 0.05Mn 1.9O 4 (M = Mg and Al) as a cathode material for lithium-ion batteries by co-precipitation method

We show 39 % reduction of amplification power consumption with cladding pump MC-EDFA using 16-core spectral superchannels over SDM NSFNET16 topology. Impairment aware least wavelength bandwidth routing algorithm further reduces the power consumption by 45%.

Various data acquisition systems have been developed based on the time-interleaved analog-to-digital converter (TIADC) technique, in which digital calibration is typically implemented on field-programmable gate arrays (FPGAs). However, FPGA-based TIADC systems suffer from high power consumption, high implementation complexity, limited hardware resources, and low integration efficiency. In this work, we propose a systematic design method to reduce the resource consumption of TIADC systems. By analyzing the characteristics of filter coefficients and optimizing allocation of computational errors, a resource-efficient digital calibration filter is proposed, achieving over 80% reduction in area and power consumption. A multi-phase sampling clock generation circuit with adjustable delay is integrated to simplify system implementation and provide coarse timing mismatch adjustment. Furthermore, the proposed architecture supports calibration of high-speed ADCs with different resolutions. To validate the proposed approach, a prototype application-specific integrated circuit (ASIC) was implemented in a 130nm CMOS technology. The chip is designed to interface with up to four 5-Gsps ADCs and consumes 11.5W of power. Simulation and analysis results demonstrate that broadband mismatch errors can be effectively calibrated by the ASIC. According to the scaling model, if fabricated in a process node comparable with that of modern FPGAs, the ASIC would achieve more than 90% reduction in power consumption relative to FPGA-based implementations consuming several tens of watts, while also lowering the implementation complexity of the TIADC system.

The interconnects have become main element in dynamic power dissipation in a Network on Chip (NoC) design. Though there have been much work on reduction of switching activity in a link, few techniques have been discussed in serial coding. In SILENT coding, the effectiveness of data dependent technique is studied. In this paper, a data independent technique is proposed in which number of switching transitions in a data word is brought down to a threshold level by rearranging data bits. To verify the efficacy of the proposed technique, encoder and decoder structures are designed using the proposed technique and described in RTL level in Verilog HDL, synthesized and mapped into UMC180 nm technology library. Proposed technique offers a maximum reduction in dynamic power consumption of 45.92%. In cases where the correlation between successive data bits is low, SILENT coding introduces an overhead in peak power consumption. It is proved that application of proposed technique with SILENT coding eliminates this overhead. The static power dissipation in proposed structure is negligible and can be easily compensated by reduction in power consumption in NOC links. In comparison with simple structure of SILENT encoder there is an overhead area of about 41.2% in structure of encoder. Proposed encoder was analyzed with various types of data streams and results confirm that unlike SILENT coding, significant power reduction is guaranteed in all the cases.

This paper explores advanced techniques for optimizing efficiency in synchronous sequential circuit design. Synchronous sequential circuits play a crucial role in digital systems, and enhancing their efficiency is paramount for achieving higher performance and lower power consumption. We delve into the difference and the advantages of multiphase clocking over single phase clocking like reduced conductor size etc. state minimization techniques to a specific sequential circuit design reduced the number of flip-flops by 20%, leading to an estimated 15% reduction in power consumption and implementing clock gating techniques in a sequential circuit design resulted in a 30% reduction in dynamic power consumption during idle periods. Through comprehensive analysis and experimentation, we demonstrate the effectiveness of these techniques in improving circuit performance and reducing resource utilization. Our findings provide valuable insights for designers seeking to push the boundaries of efficiency in digital circuit design.

An energy efficient double logarithmic arithmetic (DLA) technique is proposed for 3-D graphics applications. DLA manipulates the logarithmic arithmetic and improves the architecture for the realization of the transcendental functions and the advanced lighting model using energy efficient techniques. The DLA features complete elimination of multipliers in logarithmic domain by using successive logarithmic converters. DLA demonstrates up to 56% reduction in power consumption as compared to the existing techniques. The main advantage of this approach is the ability to perform the complex functions using power-efficient, area-efficient, as well as high frequency design. The proposed technique performs transcendental functions using multiplier free hardware architecture. Moreover, based on nonuniform subdivisions and piecewise linear approximation, novel logarithmic and antilogarithmic converters are also proposed. These converters achieve optimal power consumption as compared to several recent approaches. The proposed converters provide low relative error with less nonuniform subdivisions. Up to 19%, 12%, and 20% reduction in relative error, area, and power consumption are achieved, respectively.