Abstract
Conventional automatic test-pattern generation (ATPG) cannot effectively handle designs employing blocks whose implementation details are either unknown, unavailable, or subject to change. Realization-independent block testing for cores (RIBTEC), a novel ATPG program for such designs, is described, which employs a functional (behavioral) fault model based on a class of nonexhaustive test sets. Given a circuit's high-level block structure, RIBTEC constructs a universal test set (UTS) for each block from its functional description in such a way that realization independence of the blocks is ensured. Experimental results are presented for representative datapath circuits, which demonstrate that RIBTEC achieves very high fault coverage and an exceptionally high level of realization independence. We also show that RIBTEC can be applied to designs containing a class of small intellectual property (IP) circuits (cores).
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