Real-time windowing in imaging radar using FPGA technique

Remote sensing systems, such as SAR usually apply FM signals to resolve nearly placed targets (objects) and improve SNR. Main drawbacks in the pulse compression of FM radar signal that it can add the range side-lobes in reflectivity measurements. Using weighting window processing in time domain it is possible to decrease significantly the side-lobe level (SLL) of output radar signal that permits to resolve small or low power targets those are masked by powerful ones. There are usually used classical windows such as Hamming, Hanning, Blackman-Harris, KaiserBessel, Dolph-Chebyshev, Gauss, etc. in window processing. Additionally to classical ones in here we also use a novel class of windows based on atomic functions (AF) theory. For comparison of simulation and experimental results we applied the standard parameters, such as coefficient of amplification, maximum level of side-lobe, width of main lobe, etc. In this paper we also proposed to implement the compression-windowing model on a hardware level employing Field Programmable Gate Array (FPGA) that offers some benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. It has been investigated the pulse compression design on FPGA applying classical and novel window technique to reduce the SLL in absence and presence of noise. The paper presents simulated and experimental examples of detection of small or nearly placed targets in the imaging radar Paper also presents the experimental hardware results of windowing in FM radar demonstrating resolution of the several targets for classical rectangular, Hamming, Kaiser-Bessel, and some novel ones: Up(x),

In this paper, the development of FPGA-based ANNs is presented. Field programmable gate arrays (FPGA) based artificial neural network (ANN) is now becoming a focus of ANN research. According to the parallelism and nature features of neural network (NN), the hardware implementation is superior comparing with software approach because it can take advantage of these characteristics. Furthermore, since FPGA is a digital device that owns reprogrammable properties and robust flexibility, many researchers have made great efforts on the realization of NN using FPGA technique. However, they encountered many problems during the process. Results of the researches are presented and discussed. The future development of FPGA implementation of ANN is also prospected. Firstly, the introduction of ANN and FPGA technique is briefly shown in this paper. Then ANN implementation with hardware, mainly FPGA, is presented and discussed

To improve the weak target detection ability in radar applications a pulse compression is usually used that in the case linear FM modulation can improve the SNR. One drawback in here is that it can add the range side-lobes in reflectivity measurements. Using weighting window processing in time domain it is possible to decrease significantly the side-lobe level (SLL) and resolve small or low power targets those are masked by powerful ones. There are usually used classical windows such as Hamming, Hanning, etc. in window processing. Additionally to classical ones in this paper we also use a novel class of windows based on atomic functions (AF) theory. For comparison of simulation and experimental results we applied the standard parameters, such as coefficient of amplification, maximum level of side-lobe, width of main lobe, etc. To implement the compression-windowing model on hardware level it has been employed FPGA. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal, pulse compression and windowing employing FPGA's. Classical and novel AF window technique has been investigated to reduce the SLL taking into account the noise influence and increasing the detection ability of the small or weak targets in the imaging radar. Paper presents the experimental hardware results of windowing in pulse compression radar resolving several targets for rectangular, Hamming, Kaiser-Bessel, (see manuscript for formula) functions windows. The windows created by use the atomic functions offer sufficiently better decreasing of the SLL in case of noise presence and when we move away of the main lobe in comparison with classical windows.

Good range resolution can be achieved with a shorter pulse. But on the other hand, shorter pulses need more peak power. The shorter the pulse gets, the more should its peak power be increased so that enough energy is packed into the pulse. High Peak Power makes the design of transmitters and receivers more difficult since the components used to construct these must be able to withstand the peak power. One way to overcome the problem of high peak power is to convert the short pulse into a long one and using some form of modulation to increase the bandwidth of the long pulse so that the range resolution is not compromised. This technique is called Pulse Compression and is used widely in Radar applications where high peak power is undesirable. This paper introduces a new radar pulse compression system, using a type of Linear Frequency Modulation (LFM) signal which lacks components around zero frequency. A core structure of a pulse processor is similar to a standard matched filter, modified to suit the application. Flexibility in the design permits the use of multiple code types and lengths needed, which eliminate ambiguities, caused by high pulse repetition frequencies. The device used in this application is a field programmable gate array (FPGA) which has distinct advantages compared to other application specific integrated circuits (ASIC) for the purposes of this work. The FPGA provides flexibility, for example, full reconfiguration in milli-seconds and permits a complete single chip solution.

Many researchers have work on the preprocessing of biomedical signal. Main objectives of these algorithms are to minimize noise and artifacts existing with these signals, so that it will be easy to analyze and diagnosis human diseases. This paper is presented a proposed digital filter design using sampling rate conversion (SRC) system for biomedical signal processing with Field Programmable Gate Array (FPGA). This proposed digital filter has advantages on simple structure, stationary response and adaptively with embedded microprocessors. Another important advantage to FPGA to digital filter implementation include higher sampling rate as compared to traditional DSP chips. The proposed system is tested on computer programmable on Xilinx ISE Suite 14.7 or Quartus II software with interface ALTRA Cyclone DE II board of FPGA device. FPGA technique is flexible and provide better performance as compared to traditional techniques. To testify this chip, we use Brian computer Interface (BCI) machine data like Electroencephalography (EEG).

In the past few years, there has been significant progress in the communications and computer technology, which requires stable, clear video image display. On the other hand, conventional analog video processing method, due to its intrinsic limitations, can not meet the requirement of high quality and high speed operation. Meanwhile, the digital video processing technique that integrates with the computer technology is growing rapidly. In this paper, we introduce the art of FPGA (Field Programmable Gate Array) that has been widely used for video signal processing, and develop the video signal acquisition and processing system that based on FPGA, thereby achieve real-time video signal acquiring, processing, and transferring.

A limited telemetry rate combined with a large amount of scientific information retrieved from the camera systems of the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter demand that classical ground processing steps like determination of scientific parameters need to be performed already on-board. Field-Programmable Gate Arrays (FPGAs) with large logic density provide a highly flexible platform to implement such sophisticated capabilities. Specifically, radiation tolerant space suitable SRAM-based FPGAs have significantly improved flexibility of high reliable systems for space applications and have already been proven in many space missions. Furthermore, the potential of SRAM-based FPGAs to support dynamic (partial) reconfiguration allows a flexible use of the available hardware (HW) platform in a TimeSpace Partitioning (TSP) manner. For the PHI Data Processing Unit (DPU), the seamless reconfigurability of these FPGAs enables multiple use of the FPGA resources during different modes of operation, i.e. one dedicated configuration for image acquisition and a different configuration for subsequent data processing. Other advantages like enhanced flexibility of a system or in-flight adaptation to changing mission requirements are presented. The basic structure proposed for the PHI DPU design is based on the results of the ESA study for a Dynamically Reconfigurable Processing Module (DRPM). The communication architecture employs our own SpaceWire based System-on-Chip Wire (SoCWire), which is able to connect reconfigurable modules to a host system with the capability to isolate these modules logically and physically. For safe in-flight update data integrity of the uploaded HW code must be guaranteed from ground upload until storage in configuration memory to maintain system qualification. This is taken into account especially in view of possible Single Event Upsets (SEUs) errors in configuration memory. A reasonable separation of the required functional modules in different configurations for the FPGAs is shown. The necessary reconfiguration of the FPGAs has no operational impact. Finally, a comparative summary of needed resources clearly outlines the advantages of a dynamically reconfigurable configuration, resulting in mission cost reduction.

Technology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs). Meanwhile, due to a number of constraints, e.g., short time to market, fickle market demands, and high non-recurring engineering (NRE) costs to name a few, Field Programmable Gate Arrays (FPGAs) have gained popularity to implement SOC designs. The applications in an SOC can be dynamically started and stopped thus forming multiple use-cases. The applications can also have diverse Quality-of-Service (QoS) constraints ranging from non real-time to soft, firm, and hard real-time constraints. At the same time the IP cores in an SOC are heterogenous in nature and run at diverse clock frequencies. The IPs can be microprocessors, DSP slices, memories, and ALU units, etc. The increasing number and diversity of applications and IPs require a powerful onchip communication architecture for quick integration and appropriate QoS. In contemporary FPGAs the onchip interconnect would be soft, i.e., programmed in the configurable fabric. The above-mentioned application and architecture trends have triggered a series of problems. (1) An increasing number of applications on an FPGA often requires dynamic reconfiguration of an application, which in turn can produce interference with other running applications. (2) The increasing complexity of an application may mean that it can not be mapped entirely on the FPGA, which in turn can encounter loss of state of data during intra-application dynamic partial reconfiguration. (3) The diverse natures of applications make it difficult to fulfill the Quality-of-Service constraints of an application. (4) Similarly, it is hard to achieve (physical) timing closure in an SOC, because of the increasing number and diversity of the IP cores. (5) The technology downscaling leads to FPGA architectures that are more prone to faults, e.g., configuration memories and logic elements in an FPGA can be stuck at a particular value. (6) Because communication architecture and IPs are both mapped as soft IPs in the same logic plane of the FPGA, their placement has many restrictions to allow for dynamic partial reconfiguration. In this thesis, we aim to address the above-mentioned problems by proposing the architecture and design flow of a new FPGA. As the main contribution of the thesis, we propose the FPGA architecture with a hardwired network on chip (HWNoC), and multiple test, configuration, and functional regions (TCFRs). We call it hardwired, because the NoC in an FPGA is built in silicon and not by using the reconfigurable elements. By having a HWNOC we can have a globally asynchronous locally synchronous (GALS) environment, which in turn ensures that data is not lost during inter-IP communication. The HWNOC separates the communication and computation in two disjoint planes, which alleviates restrictions on the placement of IPs. As the second contribution of the thesis, we show how we can use the HWNOC to transport unified test, configuration, and functional data to TCFRs, for testing, faster configuration, and interference-free communication during execution of applications. As the third contribution of the thesis, we demonstrate that how the proposed design flow ensures predictable application behavior by fulfilling the QoS constraints. We also present a 3-tier reconfiguration model that uses the HWNOC, which ensures contention-free communication at architecture level, to overcome the problems of interference and state-loss during inter-application and intra-application reconfiguration respectively. Another contribution of the thesis is that it proposes a non-intrusive test methodology that uses the HWNOC as a test access mechanism to test the presence of faults reliability of FPGA architecture. In other words, the proposed methodology makes sure that applications are always reconfigured and executed on a reliable region of an FPGA, and without effecting the other running applications.

A novel approach based on digital linear frequency modulation (LFM) with anti-aliasing system for adjustable compensation of the active filter frequency response has been proposed to implement high speed pulse compression on Field Programmable Gate Array (FPGA) chip. The main objectives are high speed pulse compression for high range resolution in target detection using modified Fast Fourier Transformation (FFT) input/output (I/O) data flow algorithm and innovative anti-aliasing system. Both simulation and implementation results indicate a significant compensation in the anti-aliasing filter response. The modified FFT method eliminates the drawbacks for implementation of pulse compression in previous works.

Hardware virtualization is a well known technique in processor based hardware architectures for abstraction of the complexity of an underlying hardware from the programmer. Not only processor based hardware, especially Field Programmable Gate Arrays (FPGA), comes with a high complexity and the exploitation for developers suffer from this fact. Each change in the hardware e.g. through an introduction of a new series results in a re-design of the applications. Therefore, a novel concept for FPGA hardware virtualization is introduced in this paper. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent from the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform, describes the tool chain for the virtual FPGA and introduces with Core Fusion a novel technique that improves the utilization of the virtual FPGA.

<strong>Problem statement:</strong> Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. <strong>Approach:</strong> The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun’s multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using Analysis Of Variance (ANOVA) method using the software Statistical Package for Social Science (SPSS) with a 0.05 confidence level was used to compare the FPGA devices. <b>Results:</b> The FPGA resource utilization by Virtex-5 is the lowest in value for 4×4, 6×6, 8×8 and 12×12-bit Braun’s multipliers as compared to Spartan-3AN, Virtex-2 and Virtex-4 FPGAs. The average connection delays in Virtex-2 shows consistency and gradual increase in value as the size of multiplier increased. Virtex-2 FPGA demonstrates lower average connection delays as compared to Spartan-3AN, Virtex-4 and Virtex-5 FPGAs. For the maximum pin delay same observations are obtained for Virtex-2 FPGA. The anomalies in maximum pin delay and average connection delay are observed in Virtex-5, Virtex-4 and Spartan-3AN FPGAs. FPGA devices also demonstrate that as the size of multipliers increases their mean latency value is also increases. <b>Conclusion:</b> The FPGA resource utilization by Virtex-5 is the lowest in value for 4×4, 6×6, 8×8 and 12×12-bit Braun’s multipliers as compared to Spartan-3AN, Virtex-2 and Virtex-4 FPGAs. Even value obtained for Virtex-5 FPGA for 4×4 bit standard Braun’s multiplier for number of occupied slices and look up tables are lower in value than reported in literature.

In this paper, Field-Programmable Gate Array (FPGA) implementation-based image demosaicing is carried out. The Newton Gregory interpolation algorithm is designed based on FPGA frame work. Interpolation is the method of assessing the value of a function for any in-between value of self-regulating variable, whereas the method of computing the value of the function outside the specified range is named extrapolation. The natural images are collected from Kodak image database and medical images are collected from UPOL (University of Phoenix Online) database. The proposed algorithm is executed on using Xilinx ISE (Integrated Synthesis Environment) Design Suite 14.2 and is confirmed on Xilinx Virtex-5 FPGA board. The main aim of this paper is to develop a demosaicing method based on the FPGA technique. Implementing image processing on hardware reduces the cost and make simpler for debugging and verification. The hardware implementation in this system gives the better quality of output image. Implementing image processing on hardware reduces the cost and makes simpler for debugging and verification. Newton- Gregory interpolation technique produces the full resolution of green channel with red and blue channels. The experimental result clearly shows that proposed Newton-Gregory interpolation-based image demosaicing outperformed other algorithms. FPGA implementation attains the maximum Peak Signal-To-Noise Ratio (PSNR) of 40.53 dB and MATLAB (Matrix Laboratory<b>)</b>. implementation attains the maximum PSNR of 38.15 dB.

The configuration data sequence of a Field Programmable Gate Array (FPGA) is an Intellectual Property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the Dynamic Partial Reconfiguration (Dynamic PR) feature of an SRAM-based FPGA with the Public Key Cryptography (PKC) to protect the FPGA configuration files without the need of fixed key storage on FPGA or external to FPGA. The proposed method, is secure against the known attacks such as the Man-In-The-Middle (MITM) attack and replay attack. Therefore, the method can be used for secure deploying of IPs from local and remote vendors. Also, using this novel method not only high-end FPGAs but also low-end FPGAs with PR capabilities are secured.

The usage of Field Programmable Gate Arrays (FPGAs) in resource-constrained devices depends on energy consumption optimization techniques. Existing techniques to reduce FPGA's energy consumption have been based on several levels of abstraction, from new transistor technologies to mapping algorithms present in circuit CAD tools. However, those techniques often fail to integrate in the CAD flow a multi-step optimization. This work proposes a bio-inspired technique, called AntES (plAcement, pipeliNing and reTiming for Energy Saving), that integrates the FPGA CAD flow joining placement, pipelining and retiming steps in order to reduce energy consumption for supporting BANs. The AntES placement performance is compared with the original VPR placement in terms of power dissipation, critical path delay and bounding box size. Results show energy consumption reduction under several benchmarks, except for the largest sequential circuits.

Pulse compression plays an important role in design of the radar system. Pulse compression using linear frequency modulation techniques are very popular in modern radar. The linear frequency modulation is used to resolve two small targets that are located at long range with very small separation between them. The primary focus of this paper is the time frequency analysis and generation of LFM waveform using Direct Digital Chirp Synthesis (DDCS). This approach has been implemented on a Field Programmable Gate Array (FPGA) for the Synthetic Aperture Radar (SAR) application.