Abstract
Neuromorphic systems are designed by mimicking or being inspired by the nervous system, which realizes robust, autonomous, and power-efficient information processing by highly parallel architecture. Supervised learning was proposed as a successful concept of information processing in neural network. Recently, there has been an increasing body of evidence that instruction-based learning is also exploited by the brain. ReSuMe is a proposed algorithm by Ponulak and Kasinski in 2010. It proposes a supervised learning for biologically plausible neurons that reproduce template signals (instructions) or patterns encoded in precisely timed sequences of spikes. Here, we present a real-time ReSuMe learning implementation on FPGA using Leaky Integrate-and-fire (LIF) Spiking Neural Network (SNN). FPGA allows real-time implementation and embedded system. We show that this implementation can make successful the learning on a specific pattern.
Highlights
Neuromorphic systems are designed by mimicking or being inspired by the nervous system, which realizes robust, autonomous, and power-efficient information processing by highly parallel architecture
This section proposed three methods that applied to the Remote Supervised Method (ReSuMe) learning implementation on FPGA, which are membrane potential ui at time t, a simplified Spike response model (SRM) is defined[17]
A neuron is modeled as a “leaky integrator” of its input I(t): the pre-synaptic input: the wij corresponds to the synaptic weight from a presynaptic neuron j, the kernel ε refers to the shape of an evoked Postsynaptic potential (PSP)
Summary
Neuromorphic systems are designed by mimicking or being inspired by the nervous system, which realizes robust, autonomous, and power-efficient information processing by highly parallel architecture. Remote Supervised Method (ReSuMe) is a new supervised learning method for Spiking Neural Networks. The main reason for the study of ReSuMe is the need to where v(t) represents the membrane potential at time t, τm is the membrane time constant and R is the membrane resistance. This equation describes a simple resistorcapacitor (RC) circuit where the leakage term is due to the resistor and the integration of I(t) is due to the capacitor that is in parallel to the resistor. In discrete digital sequential circuit, a linear decay method is usually used to optimize computing process for saving hardware resources. Postsynaptic Potential and Spike Response Model the learning on a specific pattern
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