RC-Term Correction in the Evaluation of Parasitic Inductances for Microwave Transistor Modelling

Abstract

Linear and non-linear microwave active devices are usually modelled with an equivalent circuit for CAD applications. The circuit is composed of parasitic (bias-independent) and intrinsic (bias-dependent) elements; the correct evaluation of both types of elements is required not only for the extraction of a non-linear model, but also for the extraction of a linear bias-dependent one, as necessary for foundry use. The evaluation of parasitics is usually performed prior to the standard full-bias measurements, for a special condition of the active device (Vds = 0, 'cold FET' measurements) [1]. The standard technique for inductances evaluation however does not take into account a correction term due to parasitic resistances and capacitances, that is equivalent to a negative inductive tern even in the low and medium frequency range, where evaluation is made. This can lead to incorrect gate, source and drain parasitic inductance values, especially for small transistors. In some cases the magnitude of the error can be comparable to the small via-hole inductance, that therefore may appear to be negative if evaluated with the standard technique; it can also represent a substantial fraction of gate and drain inductances. In this paper the underlying theory and experimental data are exposed.