Abstract
Total-dose irradiation seriously damages MOS devices and their circuit performance. Threshold voltage shifts, transconductance degradation and increase in off-state leakage current are generally observed for irradiated devices. These instabilities are essentially due to positive and/or negative charge trapping in SiO 2 and interface trap generation at the SiO 2/Si interface. Radiation hardening of CMOS VLSIs is to eliminate these trapping effects, and for this purpose, special considerations for fabrication processes and layout design are necessary. In this paper, basic mechanisms for radiation-induced charge trapping and related effects on MOS devices are reviewed. Also discussed are radiation-hardening technologies from both fabrication-process and layout-design viewpoints. Using these technologies, 1 μm radiation-hard CMOS gate arrays have been successfully developed. Experimental data taken for 2k-gate test chips indicate that radiation hardness of these gate arrays is over 1 Mrad.
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