Python facilitates the rapid prototyping and hw/sw verification of processor centric SoCs for FPGAs

Abstract

System Python (SysPy) is a public domain design tool using Python to facilitate all prototyping phases of processor-centric SoCs for FPGAs. In previous work we used Python as a high-level description mechanism to design hardware modules and connect them to embedded processors. In this paper we show how SysPy can also facilitate high-level functional verification of a SoC when used as an Architectural Description Language (ADL), helping a designer make decisions about key architectural features early in the design phase. To the best of our knowledge our tool is unique in supporting algorithmic joint modeling of hardware and software elements of a SoC (processing and control logic) using popular Python libraries such as SciPy and NumPy following a Matlab-like syntax. The tool also supports C software development and hw/sw co-verification as it automatically compiles and executes the user's C application code for the processor core. Other important features are the generation of Value Change Dump (VCD) files for visualizing signal waveforms using popular simulation tools, and of IP-XACT metadata models for presenting hardware blocks using alternative views (Python simulation models, RTL descriptions, IP-XACT models).