PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop

Abstract

In this paper, we propose a replica-based all digital delay locked loop(ADDLL). In the ADDLL, the phase detector detects the phase error, and the accumulator(ACC) determines how long the output clock leads to or delays the input clock. In addition, the analog charge pump, loop filter(LF), and voltage controlled delay line are replaced by the ACC and digitally controlled delay line(DCDL), thereby decreasing the leakage current and size of the LF. In this study, the ADDLL uses a replica DCDL to describe a technique for detecting the phase error that may be caused by changes in temperature or supply voltage after the DLL is locked. The proposed DCDL circuit works with a 180 nm CMOS process and has a power consumption of 12 MW, using a supply voltage of 1.8 V at 625 MHz. The total size of the layout is 250×300 μm.