Programmable Local Clock SET Filtering for SEE-Resistant FPGA

Abstract

This brief presents a new clock-related <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Single-Event Effect</i> (SEE) mitigation method for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Field Programmable Gate Arrays</i> (FPGAs). SEEs are most likely to happen in harsh environments, such as space, and are decently mitigated with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Triple Modular Redundancy</i> (TMR). However, clock tree triplication has a high cost for FPGAs; it reduces the total amount of usable clocks and introduces uncontrolled skew variation. Therefore, we propose to instantiate a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Programmable Local Clock Filter</i> (PLCF) close to TMRed sequential elements to locally triplicate the clock and filter the SEEs coming from the clock tree. The PLCF mitigation method has demonstrated 100% resilience to SEEs, which target either the clock tree or the PLCF’s logic. Thus, PLCF represents the first programmable clock-related SEE mitigation method and proposes a promising alternative to the state-of-the-art technics applied to FPGAs’ fabric.