Preliminary feasibility analysis of component based modelling and automatic Java code generation for nanosatellite on-board software

Wind energy has the advantages of wide distribution, renewable, and non-polluting, so it is receiving more and more attention from more and more countries. As more and more wind power systems are integrated into the grid, it has an impact on the stability of the grid. To keep the power system stable, there is an urgent need for a grid simulator that can simulate various behaviors of the grid and test the reliability of the wind turbine before grid integration. Inverters, especially multilevel inverters, as the core part of the grid simulator, have been widely studied by scholars in recent years. However, compared to conventional inverters, multilevel inverters are characterized by high code development effort, great difficulty, and a long development period. In this paper, we adopt an automatic DSP code generation method with MATLAB hardware support package and give a complete system design method and development flow based on MATLAB and TMSF28335 automatic code generation. Finally, we take the closed-loop three-level MMC inverter as an example, propose an equalization algorithm suitable for automatic code generation for the capacitor-voltage balancing part, and verify the feasibility of the DSP automatic code generation in a multilevel inverter development. The feasibility of DSP automatic code generation in the development of a multilevel inverter is verified. The experimental results show that the proposed equalization algorithm with variable reference coefficient and DSP automatic code generation method can be used in the development of a multilevel inverter, which can improve development efficiency and reduce development costs.

Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures.

"Software development is an important area in software engineering, which is why a wide range of techniques, methods, and approaches has emerged to facilitate software development automation. This paper presents an analysis and evaluation of tools for automated software development and automatic code generation in order to determine whether they meet a set of quality metrics. Diverse quality metrics were considered such as effectiveness, productivity, safety, and satisfaction in order to carry out a qualitative and quantitative evaluation. The tools evaluated are CASE tools, frameworks, and Integrated Development Environments (IDEs). The evaluation was conducted to measure not only the tools’ ability to be employed, but also their support for automated software development and automatic source code generation. The aim of this work is to provide a methodology and a brief review of the most important works to identify the main features of these works and present a comparative evaluation in qualitative and quantitative terms of quality metrics. This would provide software developers with the information they need to decide the tools that can be useful for them."

Automatic code generation based on Coloured Petri Net (CPN) models is challenging because CPNs allow for the construction of abstract models that intermix control flow and data processing, making translation into conventional programming constructs difficult.We introduce Process-Partitioned CPNs (PP-CPNs) which is a subclass of CPNs equipped with an explicit separation of process control flow, message passing, and access to shared and local data. We show how PP-CPNs caters for a four phase structure-based automatic code generation process directed by the control flow of processes. The viability of our approach is demonstrated by applying it to automatically generate an Erlang implementation of the Dynamic MANET On-demand (DYMO) routing protocol specified by the Internet Engineering Task Force (IETF).

In this paper incorporating manual and automatic code generation is discussed. A solution for automatic metadata-driven code generation is presented illustrated with multi tier Enterprise Resource Planning System. We intend to make our solution available to public in order to encourage investigation of code generation and schema-driven tools for .NET Framework.

The complexity of embedded systems design is continuously augmented, due to the increasing quantity of components and distinct functionalities incorporated into a single system. To deal with this situation, abstraction level of projects is incessantly raised. In addition, techniques to accelerate the code production process have appeared. In this context, the automatic code generation is an interesting technique for the embedded systems project. This work presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware, the authors applied the directives of OpenMP, which specifies portable implementations of shared memory parallel programs. A case study focused on the use of embedded systems for the DCT algorithm is presented in this paper to demonstrate the feasibility of the proposed approach.

<div class="htmlview paragraph">Model-based software development and automatic code generation have become increasingly established in recent years. The automotive industry has widely adopted and successfully deployed these methods in many different series production programs worldwide. This brought various benefits, such as a reduction in development times, improved quality due to more precise specifications, and early verification and validation by means of simulation.</div> <div class="htmlview paragraph">At the same time, more and more safety-related and safety-critical systems have been - and will be -introduced into modern vehicles. Common examples are active front steering, adaptive cruise-control, and integrated chassis control.</div> <div class="htmlview paragraph">This leads to the question, if and how model-based design and automatic production code generation can be applied to the development of safety-critical systems.</div>

A new technique for automatic retargetable code generation is presented. This technique is based on the observation that a ‘reduced instruction set’ subset can always be found for a target machine instruction set; the rest of the instructions are seen to be equivalent to sequence of the reduced instruction set instructions. Given a target machine description, a method is presented which partitions it into two: one partition contains the reduced instruction set; the other contains the rest of the instructions, along with corresponding simulation sequences — these simulation sequences are unique with respect to the partition. In view of the above, the code generation problem, more precisely the instruction selection problem, is seen as a sequence of two phases: The first phase generates reduced instruction set code; the second phase finds opportunities for optimization through compaction of sub sequences in the generated code, to complex instructions. The full capability of the target machine can be potentially utilized due to the latter phase. Retargetability is achieved by automatically generating the above phases from the information in the partition. The phases are based on tree-pattern-matching, implemented through LR parsing. The technique has been tested for the MC 68000; simple comparisons show the generated code to be satisfactory.

As a model-based tool, automatic code generation technology has been known and used by more and more developers due to its efficiency and convenience. This article combines UML and automatic code generation technology, proposes the conversion rules between UML model diagrams and Java code, and uses object-oriented and modular design ideas to divide the Java code automatic generator into input layer, data verification layer, and code. Generation layer, each layer uses the form of a unified interface for data exchange. Designed and implemented a Java code automatic generator based on UML model diagram. The main contents of this paper are as follows:(1)Study the mapping rules for converting UML class diagrams and sequence diagrams into Java code, extract the elements and relationships of various model diagrams, build a metamodel of UML model diagrams, and study the mapping between metamodels and Java statement-level code Relationship, and put forward sentence-level code conversion rules.(2)Using DOM, Xpath and trufun-plato plugins to parse the metadata in UML model diagrams. Through the previous study of UML class diagrams, sequence diagrams and state diagrams to the mapping rules of Java code, the coding realized automatic generation of Java code based on UML And verified the proposed Java code mapping rules.Through tests and practical use proofs, the UML model-based automatic Java code generator can convert UML model diagrams into parts of Java code, verifying the correctness and feasibility of the rules studied.

The increasing reliance on automatic code generation integrated with Generative AI technology has raised new challenges for cybersecurity defense against code injection, insecure code templates, and adversarial manipulation of an AI model. These risks make developing advanced frameworks imperative to ensure secure, reliable, and privacy-preserving code generation processes. The paper presents a novel Hybrid Artificial Neural Network (ANN)-Interpretive Structural Modeling (ISM) Framework to alleviate the cybersecurity risks associated with the automatic code generation using Generative AI. The proposed framework integrates the predictive capability of ANN and structured analysis of ISM for the identification, evaluation, and treatment of common vulnerabilities and risks in automatic code generation. We first conduct a multivocal literature review (MLR) to identify cybersecurity risks and generative AI practices for addressing these risks in automatic code generation. Then we conduct a questionnaire survey to identify and validate the identified risks and practices. An expert panel review was then assigned for the process of ANN-ISM. The ANN model can predict potential security risks by learning from historical data and code generation patterns. ISM is used to (1) structure and visualize (2) relations between identified risks and mitigation approaches and (3) offer a combined, multi-layered risk management methodology. We then perform an in-depth examination of the framework with a case study of an AI-based code generation company. We further determine its practicality and usefulness in real-world settings. The case study results show that the framework efficiently handles the primary cybersecurity challenges, such as injection attacks, code quality, backdoors, and lack of input validation. The analysis characterizes the maturity of several mitigation practices and areas for improvement for security integration with automatic code generation functionality. Advanced risk mitigation is enabled in the framework across multiple process areas, where techniques such as static code analysis, automated penetration testing, and adversarial training hold much promise. The Hybrid ANN-ISM Mechanism is a stable and flexible solution for cybersecurity risk reduction in automatic code generation environments. The coupling of ANN and ISM, in terms of predictive analysis and structured risk management, respectively, contributes effectively towards the security of AI-based code generation tools. More research is required to improve the scalability, privacy preserving, and dynamic integration of the framework with cybersecurity threat intelligence.

Automatic generation of efficient instruction code for integrated digital signal processors is addressed. Since these processors are primarily used in real-time applications, the instruction code has to meet high quality requirements. For this reason, the author is interested in generating optimal or at least highly optimized code regarding its execution time. However, in general, conventional compiler design techniques do not lead to satisfactory results because signal processors and microprocessors are very different in architecture. The algorithm for automatic instruction code generation presented here is based on a target machine description by trellis diagrams. It can be applied to generating efficient instruction code for a large number of modern integrated digital signal processors. >

Automatic Feature Extraction and CNC Code Generation in a CAPP System for Micromachining

Today embedded system development is a complex task. To aid the engineers new methodologies and languages are emerging. During the development the system is modeled using different tools and languages. Transformations between the models are traditionally done manually. We investigate the automation of this process, specifically we are looking at automatic UML to SystemC transformation. In this paper we compare UML and SystemC, focusing on communication modeling. We also present mapping rules for automatic SystemC code generation from UML. The mapping has been implemented in our UML to SystemC code generator.

Modern avionics architecture is evolving from traditional federated architecture to Integrated Modular Avionics (IMA) architecture. ARINC653 standard, which is employed in the avionics industry, supports partitioning core concept in IMA. Furthermore, avionic software has very high safety and reliability requirements in safety- critical domains. Therefore, how to develop high-integrity avionics software constructed on ARINC653 architecture becomes a very significant problem nowadays. In this paper we propose an automatic RT-Java code generation approach based on the AADL model for ARINC653 (AADL653) to enable the development of RT-Java ARINC653-based avionics software more productive and trustworthy. Our main contribution in this paper includes: (1) a mapping from the AADL653 model to a high-integrity RT-Java programming model for ARINC653 (RT-Java653); (2) an ARINC653-compliant RT-Java code generation algorithm suitable for complex multi-task collaboration interaction situation. Accordingly, we implement this RT-Java class library and corresponding code generator. Moreover, a simplified multi-task flight application as a case study is given to illustrate our approach and the preliminary experiment results show the validity of our approach.

On-target rapid prototyping uses automatic code generation to execute embedded control software, such as powertrain control systems, on close-to-production hardware. This contrasts with rapid prototyping that typically uses much more powerful hardware than will be used in production. Rapid prototyping allows the designer to evaluate the functional behaviour of embedded software, however, it does not ensure that the final product will satisfy the performance requirements on a resource constrained, mass production embedded microprocessor. By contrast, on-target rapid prototyping additionally allows an assessment of how the automatically generated code will perform on final production hardware. On-target rapid prototyping is being widely adopted in today's automotive and aerospace development processes. The primary technology that enables this is Model-Based Design with automatic production code generation. This session introduces on-target rapid prototyping. It will also discuss modelling and code generation guidelines that help developers transition smoothly from traditional rapid-prototyping to on-target rapid prototyping. Workflow details presented include model conversion from floating-point to fixed-point, data dictionary creation, block and state machine selection, and optimal code generation settings.