Power MOSFET Verilog modelling

Abstract

Power MOSFETs are electronic devices used for modern switches. The complexity of mixed-signal system-on-chip using power MOSFETs has increased. Advanced analog and digital interfaces, tough requirements for their safety and reliability impose new advanced methodologies for their simulations. Cadence Virtuoso offers a complex simulation environment including AMS, a mixed digital - analog simulation tool. Power MOSFETs behavioral models are needed for analog and digital simulations. Virtuoso AMS is a reference language in the mixed-signal environment, aimed to provide a good tradeoff between accuracy and speed in verification. This paper proposes a new approach in power MOS simulation using System Verilog for analog and digital simulation. A new model for a power transistor has been developed. The model was used for an analog simulation for a power stage circuit including a power MOSFET. The power stage was also simulated in Verilog, commonly used in the design and verification of digital circuits. The analog and digital outputs plotted in SimVision were in good agreement in order to validate the model.