Power efficient SAR ADC designed in 90 nm CMOS technology

Abstract

A 8-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is designed using non redundant SAR structure and sequencer/code Register structure for low power operation. The designed ADC structures provide optimum results for all three circuit design challenges: speed, area and power. Among the two designed SAR ADCs, non-redundant SAR structure ADC and sequence/code register SAR structure ADC is power efficient than SAR ADC designed for the same feature size. Design and simulation of various SAR ADCs has been done in 90 nm CMOS Technology.