Power‐efficient error‐resilient network‐on‐chip router using selective error correction code scheme

Abstract

In this Letter, a new error-resilient router design for network-on-chips (NoCs) is proposed to effectively address various transient errors considering power efficiency and implementation complexity. To cope with the most probable error conditions, a selective error correction code (ECC) is embraced in router design, which combines an optimised double-bit error-correcting Bose–Chaudhuri–Hocquenghem (BCH) code and a single-bit error-correcting Hamming code. To reduce the inherent delay overhead of the BCH code, the parallel BCH coding scheme is designed and implemented into the proposed router. Furthermore, the associated ECC controller is designed for switching into an appropriate ECC mode without an additional delay at runtime. The proposed router is synthesised using 28 nm CMOS technology. Experimental results with a variety of common error conditions show that the proposed method improves the average latency by up to 13.8% and achieves up to 11.5% power reduction with the area increase of 5.7%, when compared to the conventional error correction scheme.