Abstract
This paper addresses a Very Large Scale Integrated (VLSI) design problem that belongs to the NP-hard class. The Gate Matrix Layout problem has strong applications on the chip-manufacturing industry. A Memetic Algorithm is employed to solve a set of benchmark instances, present in previous works in the literature. Beyond the results found for these instances, another goal of this paper is to study how the use of multiple populations and different migration strategies affects the algorithm's performance. This comparison has shown to be fruitful, sometimes producing a strong performance improvement over single population approaches.
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