Abstract
Gallium Arsenide Integrated Circuit (IC) Technology demands extremely flat and almost “damage-free” GaAs wafers to maximize the yield in the manufacturing of ICs. These devices are fabricated on oriented surfaces of the crystals, which have been polished to a high degree of Harness and smoothness. The polishing procedures typically involve the use of abrasives successively to result in finer surfaces with a final chemical polishing step to remove the surface damage caused by the abrasives. However, if the final polishing step does not result in damage-free surfaces, local variations in the crystallographic orientation of the surface may lead to defective device structures. Extensive reviews are available in literature on the aspects of etching of GaAs substrates, including procedures for the preparation of polished substrates and on the revelation of defects by selective etchants.
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