Abstract
Arbiter is the core element in shared-resources systems such as in network-on-chip (NoC), conventional interconnection buses and computer network switch schedulers. Arbiters are located in the critical path delay (CPD) of these systems, that necessitates fast and fair arbitration. This paper proposes two gate-level arbiter architectures. The first arbiter is an improved ping-pong arbiter (IPPA) that is optimized to offer lower execution delay compared to existing round robin arbiters (RRAs). One of the main disadvantages of ping-pong arbiter (PPA) is that fair arbitration is limited to the uniformly-distributed active requests pattern. To solve this problem, we propose a new gate-level RRA, called ping-lock arbiter (PLA). PLA, which is an improved IPPA offers fair arbitration under any distribution of active requests and has the advantage of low execution delay. The FPGA and ASIC implementations of PLA show up to 18% and 12% improvement in average delay, respectively, when compared to existing RRAs in literature.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
