Pin Assignment Optimization for Multi-2.5D FPGA-based Systems

Abstract

Advanced 2.5D FPGAs with larger logic capacity and higher pin counts compared to conventional FPGAs are commercially available. Some multi-FPGA systems have already utilized 2.5D FPGAs. Commercial 2.5D FPGA consists of multiple dies connected through an interposer. The interposer provides a fraction of the amount of interconnect resources with increased delay compared to that within individual dies. A recent study has shown the benefits of reducing signal crossings between dies on routability and timing when a circuit is mapped to a 2.5D FPGA. In a multi-2.5D FPGA system with multiplexed hardwired inter-FPGA connections, there can be tens of thousands of inter-FPGA signals incident with each FPGA and their pin assignment can greatly affect the amount of signal crossings between dies. In this paper, we formulate the pin assignment problem for such system with the objective of minimizing signal crossings between dies within the individual FPGAs. Taking into consideration of the multi-die structure of 2.5D FPGA, we propose an effective and efficient iterative improvement algorithm based on integer linear programming to the pin assignment problem. Experimental results show that our algorithm can reduce signal crossings between dies in the individual FPGAs by over 30% on average compared to two heuristic approaches.