Abstract
The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 μm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.
Highlights
Device scaling, which has driven complementary metal-oxide-semiconductor (CMOS) technology for the last 45 years, increases transistor density, and that of the metal interconnects at the back end of line (BEOL)
Scaling in the BEOL means a reduction in the topological design rules (DRs) for metal line width and space, along with those for contact space (CS) and via width
A comprehensive set of layout design rules should be defined by the wafer foundry for the use of the layout engineer, P-cell, and PDK Eng’s, as well as the designers that set up the place and route (P&R) design tools
Summary
Device scaling, which has driven complementary metal-oxide-semiconductor (CMOS) technology for the last 45 years, increases transistor density, and that of the metal interconnects at the back end of line (BEOL). Electrical parameters such as line resistance (nominal value and distribution) and reliability parameters such as maximum current density to eliminate electromigration (EM) are much more difficult to achieve. This results in requirements for better process integration and better materials, and in more demand for layout design rules with supported EDA (Electronic Design Automation). Several books on the BEOL process and the related electrical and reliability aspects are available [1,6]; they do not fully cover the definition and setting of the layout design rules.
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