Abstract

In order to cope with up to two times the nominal LHC luminosity, the second level of the readout system of the CMS Drift Tubes (DT) electronics needs to be redesigned to minimize event processing time and remove present bottlenecks. The μ ROS boards are μ TCA modules, which include a Xilinx Virtex-7 FPGA and are equipped with up to 6 12-channel optical receivers of the 240 Mbps input links. Each board collects the information from up to 72 input links (3 DT sectors), requiring a total of 25 boards. The design of the system and the first validation tests will be described.

Highlights

  • In order to cope with up to a factor 2 nominal LHC luminosity, the second level of the readout system of the CMS Drift Tubes (DT) electronics needs to be redesigned to minimize event processing time and remove present bottlenecks.

  • The uROS boards are uTCA modules, which include a Xilinx Virtex7 FPGA and equip up to 6 12-channel optical receivers of the 240 Mbps input links.

  • Each board collects the information from up to 72 input links (3 DT sectors), requiring a total of 25 boards.

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Summary

Introduction

In order to cope with up to a factor 2 nominal LHC luminosity, the second level of the readout system of the CMS Drift Tubes (DT) electronics needs to be redesigned to minimize event processing time and remove present bottlenecks.

Results
Conclusion

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