Performance modeling of fault-tolerant systems using VHDL

Abstract

The authors present a methodology which creates a single-path design environment based on a hardware description language (HDL). This methodology allows high-level performance modeling and, potentially, reliability modeling to be performed using the same HDL and simulation environment that is used to perform detailed design. In fact, the significant advantage of the approach is that the same modeling language and environment can be used from conceptual design to implementation, thus avoiding the need for translate among different CAD tools. The specific HDL used is the VHSIC (very-high-speed-integrated-circuit) hardware description language (VHDL). The authors illustrate the application of the methodology to fault-tolerant system design by modeling, simulating, and evaluating the performance of a multiprocessor system with the algorithm-to-architecture-mapping-model (ATAMM) management strategy being used for resource/task allocations. >