Performance improvement of CMOS device utilizing poly-Si/HfSiON gate stack and its reliability concern for 65 nm technology and beyond

Abstract

We have developed low standby power (LSTP) FET utilizing HfSiON dielectric. Due to optimizations of channel and offset spacer structure, we could put threshold voltage of pFET into the place of LSTP region, working through the Fermi-level-pinning effect. This resulted in the reduction of propagation delay and in performance improvement of our test product. We could also introduce reverse body-biasing technique for standby leakage reduction even for LSTP device. In order to characterize positive bias temperature instability (PBTI) of nFET, we have evaluated the kinetics of the electron trapping in amorphous HfSiON (a-HfSiON) and partially crystallized HfSiON (c-HfSiON) dielectric. We have found that the difference in PBTI reflects the structural diversity between them, such as spatial and energy distribution of the traps. We need to take notice of such diversity and figure out the origin of PBTI. Phosphorus penetration into HfSiON should be avoided in terms of gate leakage increase and TDDB degradation. To suppress it, we proposed double-layer gate electrode structure, which consisted of as-deposited amorphous layer followed by poly-Si layer.