Performance comparison of KASUMI and hardware architecture optimization of f8 and f9 algorithms for 3g UMTS networks

Abstract

This paper proposes a performance comparison of 64-bit KASUMI block cipher architectures based on speed vs. area trade-offs. The analysis includes 8-rounds KASUMI architectures for high-speed designs, 2-rounds / 1-round KASUMI architecture for moderate area / throughput values and optimized one round KASUMI having one FI function for low area design requirements. A throughput value as high as 13.6 Gbps is found using ROM blocks for S-boxes whereas compact designs require an area of 2.99 NAND gates implementing S-boxes using combinational logic. The paper also focuses on the hardware architecture optimization of f8 and f9 algorithms for low power implementation of 3g mobile equipments. A novel architecture is proposed based on one KASUMI block and is employed for both f8 - confidentiality algorithm and f9 - integrity algorithm. The optimized hardware generates 32-bit MAC and the required bit-stream for encrypting every 10 msec message frame of maximum 20,000 bits. The scheme is very suitable and can be adopted for compact implementation of f8 and f9 algorithms for 3g UMTS mobile communication networks.