Performance and variability driven guidelines for BEOL layout decomposition with LELE double patterning

Abstract

Litho-etch-litho-etch (LELE) double patterning lithography (DPL) is a strong candidate for BEOL patterning at the 20nm logic half-node (sub-80nm pitch). In double patterning lithography, layout pattern features must be assigned opposite colors if their spacing is less than the minimum coloring spacing. However, complex layouts usually have features that are separated by less than the minimum coloring spacing for any coloring assignment. To resolve the minimum coloring spacing constraint, a pattern feature (polygon) can be split into two different-color segments, introducing a stitch at the splitting location. Although many DPL layout decomposition heuristics have been proposed, the impact of stitches on circuit performance is not clearly analyzed. In this work, we study the impact of stitches on BEOL electrical performance based on analytical RC equations. Our studies with 45nm (commercial) and 22nm (ITRS) technology parameters show that (1) optimal stitching location can reduce delay variation by 5%, and (2) introducing redundant stitches (i.e., splitting an interconnect segment intentionally) can potentially reduce circuit delay variation.