Performance Analysis of FinFET based Carry save Adder Cell with Predictive Technology Models

Abstract

As scaling of conventional metal-oxide-semiconductor field effect transistor is approaching its fundamental and technological limits, alternate device solutions are being developed. FinFET is rapidly replacing conventional CMOS transistors as it offer lot of improvements in power consumption, propagation delay and propagation delay product (PDP). This paper presents design & simulation of a double gate FinFET based ultra low power 2-bit Carry Save Adder (CSA) cell. A comprehensive comparison of FinFET and CMOS based 2-bit carry save adder has been performed. The CMOS & FinFET based 2-bit carry save adder circuits are evaluated at 32nm & 45nm nanoscale technology nodes using Predictive Technology Models (PTM). At 45nm technology node, the FinFET based carry save adder results shows average power consumption reduction of 39.75%; propagation delay reduction of 92.50% and a propagation delay product (PDP) improvement of 94.42% as compared to CMOS counterparts. The FinFET based carry save adder results shows average power consumption reduction of 42.19%; propagation delay reduction of 86.86% and a propagation delay product (PDP) improvement of 92.22% as compared to CMOS based carry save adder at 32nm technology node.