Performance Analysis of Dual Material Graded Channel Cylindrical Gate All Around (DMGC CGAA) FET with Source/Drain Underlap

Abstract

In this paper the effect of underlap on Dual material graded channel cylindrical gate all around FET (DMGC CGAA FET) has been investigated. Due to improved gate electrostatic control, multigate structures have greater short channel control than typical bulk devices. The DMGC CGAA FET is a potential candidate among the multi gate devices because of its ease of manufacture. The inclusion of gate underlap in the proposed device improves the short channel immunity. To further enhance the device performance different types of spacers are incorpo-rated in the underlap regions. The underlap length <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(L_{un})$</tex> was optimized at 4.5 nm for the proposed device. Simulation results shows that there is an improvement in the switching ratio <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\frac{I_{on}}{I_{off}})$</tex> , subthreshold swing (SS) and other SCEs. The DC and Analog/RF performance was investigated with different types of spacers and observed that HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> results the better subthreshold performance compared with other spacers. Sentaurus TCAD simulator was used to extract the simulation results and to calibrate the device with experimental data.