Pass-parallel VLSI architecture of BPC for embedded block coder in JPEG2000

Abstract

The embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression international standard. Various applications, such as medical imaging, multispectral imaging such as remotely sensed imagery, satellite imagery, mobile multimedia communication, 3G cellular telephony, client-server networking, e-commerce, digital cinema, and others, require high speed, high performance EBCOT architecture. EBCOT encoder consist Tier-1 (block coder) and Tier-2 coding. The block coder is further partitioned into bit plane coder (BPC) and matrix quantizer (MQ) coder. The input to BPC is quantized DWT coefficients, which are stored in code block (CB) memory. BPC produces a context and decision (CXD) pair for each bit in the CB memory. The MQ coder processes these pairs and produces a compressed bit stream. Finally, as per the user's requirement, Tier-2 organizes this bit stream and generates compressed data. Though efficient EBCOT architectures have been proposed, throughput is low. To solve this problem, we used concurrent context generation. Therefore, all samples encoded in a stripe-column concurrently. As a consequence, high throughput is attained. The entire design of BPC encoder is tested on Virtex-5 XC5VLX50-1ff676 Xilinx Field Programmable Gate Array (FPGA) platform using Verilog-HDL. This BPC architecture design can operate at 91.152MHz speed.