Particle filter implemented as a hardware accelerator in Cortex-M core periphery

Abstract

Particle filters are a group of filtering methods based on recursive Bayesian filters which can be used to estimate the state of an observed dynamical system. The main advantage of the particle filters when compared to other similar filtering methods is that it can handle a nonlinear system which includes non-Gaussian noise sources. A hardware accelerator represents a digital module which is specifically made to perform some function. The module is adapted exclusively to the designed function which the module executes more efficiently and faster than it is possible using a software implementation on a general-purpose processing core. This paper analyses a hardware accelerator which implements a particle filter used in the inertial measurement unit (IMU) measurements. The accelerator is used in periphery of a low power and low gate count Cortex-M1 core. The accelerator is evaluated with respect to the area utilization and execution performance and it is compared to a software implementation of an equivalent particle filter executed on the Cortex-M1 core. The results show that the hardware accelerator has a 30% smaller cell count than the accompanying Cortex-M1 core. The hardware implementation of the particle filter has a two-orders of magnitude shorter execution time than the reference software implementation running on the Cortex-M1 core.