Abstract
Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing power, design and manufacture of parallel processing units, has been very much considered. One of the most important processor families used in various devises is the MIPS processors. This processor family had been considered in the telecom and control industry as a reasonable choice. In this paper, new architecture based on this processor, with new parallel processing design, is provided to allow parallel execution of instructions dynamically. Ultimately, the processor efficiency to several fold will be increased. In this architecture, new ideas for the issuance of instructions in parallel, intelligent detection of conditional jumps and memory management are presented.
Highlights
MIPS processors are a group of processors based on the Reduced Instruction set Computers (RISC)
Initial versions are based on 32-bit instructions, and in later versions 64-bit support is added
Support for multithreading structures has been added to MIPS architectures
Summary
MIPS processors are a group of processors based on the Reduced Instruction set Computers (RISC). Multi-cycle architecture: In order to increase the number of instructions executed by the processor at a given time, the pipeline technique is used In this technique, the operations required to complete each instruction are divided into separate parts, and the result of each stage is stored at the beginning of each clock cycle for use in the stage. Despite the limit on the number of writing ports in the register file (two ports), it is still possible to fill in 4 multiple issues for executing instructions In this way, there are two lines for arithmetic and branch operations, a storing line and a line to load from the main memory. 3-1- Study of Structural Constraints and Dependency of Instructions for Hardware Recoding
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