Abstract
The stacked structure thin film transistors (TFT) has caused the widespread attention to achieve high mobility and reliability simultaneously. To ensure the stacked structure TFT application to mass production, it is critical to reduce the number of mask‐count. In this paper, 8‐mask‐count stacked TFT‐array process using the first semiconductor layer overlapped with the source and drain layer directly, which is the first layer on the glass substrate, is studied. By adopting this novel process, the device mobility is 25.4 cm2/Vs, which is more than twice that of conventional top‐gate self‐aligned a‐IGZO device. Besides, the ΔVth under the positive bias stress of 30V and negative bias temperature illumination stress of ‐30V for 1 h is +0.41V and ‐0.13V, respectively, achieving the stability to the level of a‐IGZO TFTs.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.