Optimizing Scheduling Technology for Clustered VLIW Architectures Using Data Dependence Graph

Abstract

Applications,especially the multimedia processing applications,have put an increasingly performance requirement on today's computer architectures.Many today's computer architectures typically are taking increasing advantage of the instruction-level parallelism(ILP) available in programs.Unfortunately,large amounts of ILP hardware and aggressive instruction scheduling techniques put large demands on a machine's register resources.With large amounts of ILP,it becomes difficult to maintain a single monolithic register file and a high clock rate.The access time for such a register file would become the bottleneck of performance improvement.To provide support for large amounts of ILP while retaining a high clock rate,registers and functional units can be partitioned into separate clusters.Register in one cluster is directly accessible by only the functional units in that cluster with specific resources required for communicating data between clusters.Therefore,a compiler must deal not only with achieving maximal parallelism via aggressive scheduling,but also with meticulous instruction placement to limit inter-cluster data communications.This work is focused on optimization of instruction scheduling technology for clustered VLIW architectures with the help of Data Dependence Graph(DDG).It reduces the amount of inter-cluster data communications and balances the use of all clusters simultaneously,and enhances the achieved instruction-level parallelism.Experiments result show that the proposing scheduling technology can largely reduce the amount of data communications among clusters,which in turn brings an improvement in achieved ILP and performance.