Optimized process simulation of USJ for HKMG DRAM periphery transistors

Abstract

An impact analysis of the various thermal budgets on the electrical trends of a HKMG-Metal Inserted Poly Si gate (MIPS) process through Technology Computer-Aided Design (TCAD) is reported. A good agreement between simulation and experimental data is shown for NMOS and PMOS FETs in a low power and low cost 45 nm technology node. The impact of the C and Ge+C co-implantation on the device performance is explored, with particular emphasis on the effects on the USJ of additional thermal treatments needed by a DRAM compatible periphery. From this understanding, further device tuning can be foreseen, in order to meet specific design requests. An application example of the optimized process simulation is shown, demonstrating the feasibility of different Vth schemes, ranging from low-power to high performance oriented devices.