Abstract
We have systematically studies designs for Modified Variable Threshold Logic Gates (MVTL) in NbN within the framework of factorial analysis. Our goal is to attain optimized margin and fanout for 10 K operation. Significant parasitic inductances, associated with current crowding at junction vias, were measured and are found to affect the operating margin. We report the progression of designs, margin measurements and yield data for our 10 K circuits. >
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