Optimization of Heterojunction Devices for High-Frequency and Low-Noise Operation

Abstract

One of the main objectives of modern Microelectronics is the fabrication of devices with increasing cutoff frequency and decreasing level of noise. At this moment, the best devices for high-frequency low-noise behavior are AlInAs/GaInAs HEMTs (InP based). In this work a complete analysis of ultra-short-gate AlInAs/GaInAs HEMTs has been performed by using a semiclassical Monte Carlo simulation. The validity of the model has been checked through the comparison of the simulated results with static, dynamic and noise experimental measurements of real 100-nm-gate HEMTs. In order to reproduce the experimental results, we have included in the model some important real effects such as degeneracy, surface charges, T-shape of the gate, presence of dielectrics and contact parasitics. We have then studied the influence of the parasitic resistances width of the devices, the number of gate fingers, the reduction of the gate down to 50 nm, together with the effect of the value of the 8-doping and the recess length With the use of computer simulations we will be able to obtain some design rules avoiding the expensive `test and error' procedure.