Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown

Abstract

Continuous memory technology scaling causes memory cells to be vulnerable to wearout. To ensure reliable operations of circuits and systems in the presence of wearout, we require accurate estimation of the lifetime of circuits and systems degraded by wearout. Since the conventional method of estimating circuit and system reliability degradation based on device-level accelerated life test (ALT) does not account for the tolerance of a circuit and a system to a wearout failure of a device, accelerated lifetime testing at the circuit and system level is necessary. For accurate estimation of system reliability using system-level ALT, we propose a method that optimizes the design of experiments for ALT. From significant observations from failure data statistics of system-level ALT with various stress conditions applied to the memory system of the Leon3 as a case study, we define acceptability regions for memory testing of each wearout mechanism. In addition, by analyzing errors in estimating Weibull parameters from system-level ALT, we develop a methodology that optimizes experimental designs in acceptability regions of each wearout mechanism to minimize such estimation errors in system-level ALT.