Optical configuration acceleration on a new optically reconfigurable gate array very large scale integration using a negative logic implementation

Abstract

This paper presents a proposal of an optical configuration acceleration method applied to optically reconfigurable gate arrays (ORGAs) using a negative logic implementation. The gate array of an ORGA is reconfigured using a holographic memory. The reading time of a holographic memory depends on the number of bright bits included in a configuration context. The proposed optical configuration acceleration method can decrease the number of bright bits. As a result, the proposed optical configuration acceleration method can increase the reconfiguration frequency. In this paper, a fabricated ORGA very large scale integration that can support the optical configuration acceleration method is estimated. Consequently, this paper shows that the reconfiguration frequency of the proposed method is 1.97 times higher than those of conventional ORGA architectures with no increase of laser power.