Abstract

Foundry services for photonic integration enable access to such technologies and facilitate fab-less businesses models. The technologies are sufficiently mature for proof-of-concept demonstrators, advanced prototypes, and two-medium small-volume production. Further improvement of the technology processes behind those services requires extensive research and development efforts in order to advance the foundry offerings and assure scalability, process control, and the yield required for volume production. A high-level automation of test and assembly processes in the PIC manufacturing chain is essential to improve statistical process control and scalability of all processes. These allow for early known-good-die identification, optimization of fabrication process window, improved yield, and volume production. In this paper we propose a standardized approach to chip layout that supports automated test and assembly processes already at the design phase. Moreover, we describe a modular test software framework based on open standards. Within this test framework, standard file formats for chip, equipment, and measurement description, and the open file formats for storage and exchange of data are described. This test framework is a part of the openEPDA initiative and enables test automation, user-defined testing, data analysis, exchangeability, and traceability across the full manufacturing chain from design to product.

Highlights

  • P HOTONIC integrated circuits (PICs) offer numerous advantages over their counterparts based on discrete components and bulk optics

  • Wireless communications, millimeter and terahertz [12]–[14], cryptography [15], [16] and quantum computing [17]–[19]. This widening range of applications of photonic ICs can be attributed to an increased availability and accessibility to photonic integration technologies via open access foundry services that are based on standardized, generic processes [1], [3], [20]

  • In this paper we propose a standardized approach to PIC layout enabling access to automated testing and generic assembly and packaging services [35]

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Summary

INTRODUCTION

P HOTONIC integrated circuits (PICs) offer numerous advantages over their counterparts based on discrete components and bulk optics. Wireless communications, millimeter and terahertz [12]–[14], cryptography [15], [16] and quantum computing [17]–[19] This widening range of applications of photonic ICs can be attributed to an increased availability and accessibility to photonic integration technologies via open access foundry services that are based on standardized, generic processes [1], [3], [20]. The MPW runs enable a seamless path to design and fabrication of application specific photonic integrated circuits (ASPICs), Fig. 1 Characterization of a sample that follows the standardized layout, is carried out according to a user-defined test sequence

STANDARDIZED LAYOUT TEMPLATES
OPEN TEST FRAMEWORK
Software Modules
Configuration Files
OPENEPDA DATA FILE FORMAT
Data Exchange
Standardized File Format
SEMI-AUTOMATED DIE MEASUREMENTS
Findings
CONCLUSION
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