On-Line Signature Learning and Checking

Abstract

This paper presents a new approach to concurrent error detection in multiple processor systems using on-line signature analysis. In this new technique, called On-line Signature Learning and Checking (OSLC), the block identification and the reference signature generation are performed at run time. Many hardware control signals are included in the signatures, which improves the error detection coverage, and the alterations and/or extensions in the compilers, assemblers and loaders are avoided. In OSLC the signatures are stored in the local memory of a watchdog processor, the Checker, which is based on a new principle that reduces the storage requirements of control flow information to less than 2% of the signature overhead. Furthermore, the Checker is very simple and can check several processors concurrently. A demonstration system of this technique has been designed and built. Results of fault injection experiments have shown that 99.4% of instruction type faults can be detected by OSLC with a very short latency (26 μSec). The coverage for general faults is 94.5% and the average latency is 464 sec.