On-chip adaptive components for balanced computing

Abstract

The demand for more on-chip computing resources to effectively execute compute-intensive functions is ever increasing. On the other hand, design of an effective register file architecture is becoming a bottleneck for meeting the memory-bandwidth demand of modern wide-issue superscalar processors. A need for a balance in the memory-bandwidth and the computing rate is significant to achieve a higher processor throughput. Further, at the advent of mobile and ad-hoc computing, processors are being expected to consume lesser amounts of energy even while delivering higher performance. This dissertation aims to address the above issues in the context of reconfigurable architectures, by exploiting the possibility of using on-chip memory elements as computing units. This enables an efficient utilization of silicon real-estate on the chip. First, this dissertation proposes TriBank Register file architecture, a novel register file organization for wide-issue superscalar processors. The organization exploits long latencies in the lifetime of a register to meet the two requirements of a small register access time and a large memory bandwidth. Next, the dissertation proposes Adaptive Register File Computing (ARC) unit, a novel on-chip processing element that leverages application-specific processing capabilities. The ARC unit supplements a conventional register file to provide large memory bandwidth, or acts as a configurable computing unit to provide higher on-chip computing capacity; depending on the requirement of a specific application. The dissertation also explores the ability of the reconfigurable computing models in delivering high performance while providing with significant savings in the energy dissipation in the various on-chip components of the processor. For the Reconfigurable Computing Cache (RFC) based processor, developed earlier to utilize a module of an L1 data cache is used as a coprocessor to process compute intensive multimedia applications, the impact of RFC on cache access time and energy dissipation has been explored. It also gives a detailed analysis on the performance of the RFC based processor in terms of the execution time of application for various configuration schemes, including the study of the effect of the percentage of the core function in an entire application over the management of RFC modules.