On the Realization of Electronically Tunable Voltage‐Mode Instrumentation Amplifier Employing a Single Voltage Differencing Current Conveyor

This research paper brings an instrumentation amplifier (IA) that exhibits all possible mode specifically voltage, current, transadmittance, and transimpedance mode using a single differential voltage current conveyor (DVCC) and few active resistors using transistors. The proposed design offers high range of 3 dB frequency for both differential gain (Ad ) and common mode rejection ratio (CMRR). The introduced topology of different IA are analyzed and simulated with PSPICE using 0.18 µm CMOS technology parameter for the realization of DVCC. Also, the experimental verification using commercially available Current Feedback Operational Amplifier (CFOA) named as IC AD844 is used to check the practical feasibility of proposed design. Apart from the ideal analysis of IA, nonidealities of the proposed work, temperature-dependent variation that affects the nature of IA, Monte Carlo simulations are well depicted in this report.

Humidity sensor can be defined as a device, which consists of plastic material whose characteristics change as per the amount of humidity present in the air. Its various application areas include controlling of the climate, storage of food articles, domestic applications etc. The reference paper implemented the humidity sensor uses post-CMOS processing of CMOS fabricated chips to obtain suspended and thermally isolated diodes. However, the paper does not include the read out circuit and the design of op-amp. Industry however always considers the design under PVT (process, voltage & temperature) variations to make it commercial. This paper aims in designing op-amp, which is used in the read out circuit of the CMOS humidity sensor based on PVT variation (process, voltage and temperature variation). The design issues for switch capacitor used in the humidity sensor are also described. The thermal design equations for the sensor diode model have also been considered and presented.

In this work, a novel general circuit configuration for realizing differential-mode first-order all-pass and second-order all-pass/notch filters with high common-mode rejection ratio (CMRR) is presented. The proposed circuit is based on a differential voltage current conveyor (DVCC). The circuit uses only one resistor and three capacitors for realizing a first-order allpass filter and three resistors and three capacitors for realizing second-order allpass/notch filter. The non-ideality analysis of the configuration is given. SPICE simulation results are included to verify the theory.

In this paper, a high Common-Mode Rejection Ratio (CMRR) and low power CMOS Instrumentation Amplifier (IA) for use in Bio-impedance Spectroscopy (BIS) is presented. It consists of a complementary Differential Voltage - Current Conveyor (DVCC) that provides the common-mode signal rejection and high input impedance, a Folded - Cascode Operational Transconductance Amplifier (FC-OTA) that serves as a gain stage, and a high pass filter built using a PMOS pseudo-resistor. The IA was implemented using TSMC 0.35µm 2P4M Polycide Technology and simulations were carried out using HSPICE. The designed IA features a CMRR of 120.2dB, a differential input impedance of 102.3MΩ, and a common-mode input impedance of 41.3MΩ both at 50kHz, while dissipating an average static power of 290µW.

The Differential Voltage Current Conveyor (DVCC) with its two polarities namely DVCC- and DVCC+ are reviewed together with their pathological element representations. Their two adjoint building blocks are the Balanced Output Current Conveyor (BOCCII) and the Balanced Output Inverting Current Conveyor (BOICCII) are also discussed with their pathological element representations. The universal CMOS circuit realizing these four building blocks is also included. The Nodal Admittance Matrix (NAM) stamp for the DVCC-, DVCC+, BOCCII and BOICCII are also given. Among the four basic building blocks considered the DVCC- is the only floating building block. Examples are given showing that some of the reported filters are related to each other by the adjoint network theorem.

Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

In the paper, a universal preudo-differential second-order filter operating in voltage mode, where both intup and output are differential, is presented. The circuit is formed by one differential difference current conveyor (DDCC), two differential voltage current conveyors (DVCCs), and five passive elements. The filter is characterized by high input impedance, minimum number of passive elements that are all grounded, and high common-mode rejection ratio (CMRR). The proposed filter structure is able to realize all five standard frequency filter responses. Non-ideal analysis has been performed by considering the real parasitic parameters of the active elements. The optimization of passive element values has been done in terms of minimal shift of the pole-frequency and to obtain the maximum stop-band attenuation of the high-pass filter response. Functionality is verified by simulations and experimental measurements using readily available integrated circuit UCC-N1B 0520. DOI: http://dx.doi.org/10.5755/j01.eie.23.6.19694

The conventional current-feedback op-amp (CFOA) exhibits high speed and high bandwidth but has relatively poor common-mode rejection ratio (CMRR) and poor DC offset and low frequency gain accuracy. Several design techniques improving the DC performance have been published. The proposed technique presented in this paper is to bootstrap the input stage with the input signal. By using this technique, the Early-effects in the input stage are almost eliminated, and as a result the DC performance including the CMRR is substantially improved. By virtue of the improved DC and CMRR performance, the gain accuracy is increased by about ten times. All of the improvements are obtained without apparent increase in the circuit size and power consumption, and consequently without degrading the noise performance.

As the process technology scaling, the tolerance to PVT (process/ voltage/temperature) variation has become a serious concern. During the post-silicon stage, ADBs (adjustable delay buffers) can be used to adjust the delay of the clock path for eliminating the clock skew. However, in fact, unless that the clock tree has a self-correcting mechanism, the clock skew caused by PVT variations still cannot be properly controlled. In this paper, we propose the first self-correcting ADB system to control the clock skew during circuit execution. Experimental results show that our design methodology can achieve very good results.

This paper presents the design and post layout simulation for electromyogram (EMG) front-end. The architecture is characterized by ultralow power consumption and gain reconfigurability. Three stages are designed to form the whole front-end. The first stage is extremely efficient single ended amplifier. The second stage is programable gain differential ended amplifier, to enhance the overall supply rejection ratio, common mode rejection ratio and the dynamic range. Finally, the third stage is a buffer stage to isolate the loading from the amplifier. The first two stages are designed with cascode MOSFETs to increase the midband gain. The full design was post-layout simulated using 130 nm CMOS technology. The results show that the design has 60.36 dB mid-band gain in range of 5.3 Hz to 1.72 kHz. Using a supply voltage of 1.1 V, the first two stages consume $\pmb{1.06\mu A}$. The input referred noise is $2.95\mu \mathrm{V}_{\mathrm{rms}}$. The common mode and power supply rejection ratios are above 94.5 dB and 79.4 dB respectively.

This paper introduces a design for an ultralow-power electromyogram (EMG) signal amplifier with low noise operation. The design consists of two stages, the first stage is highly efficient but supply-sensitive single ended amplifier and the second stage is differential, to improve the supply rejection ratio and common mode rejection ratio. Each stage is configured with cascode MOSFET transistors to increase the gain value. The proposed design is simulated by 130 nm CMOS, and its results are reported. The design achieves 60.62 dB mid-band gain with bandwidth of 1.72kHz. Using a supply voltage of 1.1 V, the amplifier consumes 1.03 μA of current. Input referred noise is 3.006 μVrms. The common mode and power supply rejection ratios are above 49.05 dB and 55.72 dB respectively.

The comment is related to the recently published paper given in [1] dealing with the implementation of series and parallel R-L and C-D impedances using a single differential voltage current conveyor (DVCC). Nevertheless, straightforward analysis of the circuit in Fig. 3(b) of [1] and also given in Fig. 1 shows that it has a problem because it makes its input voltage V in = 0. Therefore, it can not realize parallel (---L)---(---R) simulator as claimed in [1]. Alternatively, a circuit given in Fig. 2 for realizing parallel (---L)---(---R) simulator employing a single minus-type DVCC (DVCC---) and a minimum number of passive components is proposed. The introduced circuit employs a grounded capacitor, and requires no critical component matching constraints thus it is suitable for fully integrated circuit technology. If plus-type DVCC (DVCC+) is replaced instead of the DVCC---, this proposed simulator can realize parallel (L)---(R) simulator. Fig. 1 The circuit proposed in Fig. 3(b) of [1] Fig. 2 Presented circuit for realizing parallel (+L)---(+R) and parallel (L)---(R) simulators depending on the type of the DVCC

In this paper, a comparative study between performance of BJT and CMOS technologies is performed by implementing two novel BJT and CMOS differential voltage current conveyors (DVCCs) with minimum and equivalent sizes. In this study, “size” means the number of the transistors used in a design. The CMOS-DVCC consists of only 12 MOS transistors, and the BJT-DVCC includes 13 BJTs. The implementations are performed in Proteus-7 environment, and the two DVCCs are formulized with their real parameters. The two chips are modeled at low frequency, and it is shown that the CMOS-DVCC has acceptable performance and behavior to operate as a DVCC while the parameters of the BJT-DVCC are far from an ideal DVCC, so the CMOS-DVCC can be used to design electronic devices. The comparative analysis shows to achieve a reliable and acceptable BJT implementation of a DVCC, it is inevitable to increase the size of the BJT implementation. To prove this claim, another novel acceptable BJT-DVCC with larger size is presented and modeled. It is also demonstrated that the acceptable BJT-DVCC is also the first and only DVCC reported in the literature which is applicable to high-power applications, and this is the other contribution of this work.

This paper presents an operational-transconductance-amplifier (OTA) for ultra-low power applications with high CMRR (common mode rejection ratio) and PSRR (power supply rejection ratio). The proposed OTA is a three-stage design. In order to attain the lower supply voltage and high CMRR, a bulk-driven differential pair with the tail current source has been considered as the first stage. The current mirror biasing technique makes sure that all the transistors operate in subthreshold region. A common source amplifier has been opted with current mirror as a load in second stage. At last, common source inverting amplifier is third stage of the designed OTA. The circuit has been designed and synthesized using cadence virtuoso simulator in 180 nm CMOS technology. It has been found that these stages are helpful in achieving high low-frequency gain. Hence, CMRR and PSRR also increase in significant amount. The results describe that the proposed design offers low-frequency gain of 58 dB with CMRR of 72 dB and PSRR of 56 dB for a supply voltage (\( V_{DD} \)) of 0.5 V. The proposed OTA provides the power dissipation of 1.8 µW at \( V_{DD} \) = 0.5 V. Also, the low-frequency gain of 57 dB, CMRR of 70 dB and PSRR of 55 dB with a power dissipation of 2.5 µW have been measured at \( V_{DD} \) = 0.6 V.

In this paper, an instrumentation amplifier (IA) based on operational amplifiers (op-amps) for biomedical applications is presented. Such IA achieves high gain and high common-mode rejection ratio (CMRR) while maintaining low power consumption, high power supply rejection ratio (PSRR) as well as other design constraints. The IA uses three identical two-stage telescopic cascode op-amps at the input and output stages. The feedback networks are comprised of resistors and capacitors, which are different from those in conventional voltage mode IA. The resistive feedback is utilized in the input stage to increase the stability while the capacitive feedback is employed in the output stage to filter undesired frequency components and enhance the gain of the IA. The schematic of IA is designed and simulated under 180 nm CMOS technology using Cadence Spectre tool. The gain and CMRR of the single op-amp are 100.45 dB and 94.8 dB respectively. The power consumed by each op-amp is 12.96 $\mu \mathrm{W}$ at a supply voltage of ± 0.9 V. RC Miller compensation technique helps the op-amp reaching a phase margin of 60°. This IA consumes a power of 38.88 $\mu$W and CMRR of 147.68 dB, with a gain of 101.61 dB. The proposed technique is suitable for a variety of biomedical applications due to its high gain and high CMRR.