On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory

Abstract

Multi-level per cell (MLC) technique has been widely used to improve the storage density of NAND flash memory. In current design practice, bits stored in one cell are mapped to different pages, and all pages are protected with the same error correction code (ECC). However, those bits in one MLC flash memory cell have different error rates, and such unbalance increases with the number of bits in one cell. To guarantee the storage integrity, ECC should be tuned to cover the worst case page, which results in over-protection and redundancy waste for other pages and hence reduces storage capacity. This bit-to-cell mapping scheme also limit the number of bits in one cell to be integer. This paper proposes an aggregated page programming scheme, which maps all bits in one cell into the same page, to balance all pages to experience the same but lower overall bit error rates, so that the weaker ECC with higher coding rate can be employed. Furthermore, the noise margin of NAND flash memory cell decreases with program/erase cycling. To exploit such noise margin dynamics, this paper proposes to accommodate more storage levels in one cell during its early lifetime and dynamically modulate the number of storage levels to increase the overall effective storage capacity. Not-a-power-of-2 storage levels in one cell should be used to exploit the storage capacity aggressively, which can be enabled through proposed aggregated page programming scheme. Simulation results show the program capacity can be increased by more than 50 %.