Offset and Gain FPN Calibrated Linear-Logarithmic Image Sensor With Shared Pixel Architecture

Abstract

This brief presents offset and gain FPN calibrated linear-logarithmic image sensor. Offset FPN originated from threshold voltage variation of the logarithmic conversion transistor is calibrated with Two-step charge transfer operation. Remaining gain FPN is analyzed and its root cause is investigated. The subthreshold slope difference of the logarithmic conversion transistors in the shared pixel architecture is found to be responsible for the increasing FPN in the logarithmic operation region and potentially limiting dynamic range in high illumination region. A simple modeling-based gain FPN correction method in linear-logarithmic APS using shared pixel architecture has been proposed. The prototype sensor is fabricated by using a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS image sensor process. Thanks to the proposed gain FPN correction together with offset correction using Two-step charge transfer operation, wide dynamic range of more than 120 dB has been achieved while maintaining the total FPN less than 0.29% over the entire dynamic range.