Abstract
This paper present a numerical validation of experimental results of Bottom Gate/Bottom Contact Pentacene transistor using SILVACO ATLAS simulator. We investigated the impact of different gate dielectric thickness on transistor performance and we estimated threshold voltage Vth, current ratio I on /I off and saturation mobility μ values. We found that gate dielectric thickness is proportional to Vth and inversely proportional to μ.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
