Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes

Abstract

Flexibility, low latency, energy-efficiency, and low area, power, and cost are very important to consider for hardware and software implementation of VLSI circuits. With the advanced technology used to design these circuits especially the System on Chip, embedded FPGA (eFPGA) is one of the fields that has attracted extensive attention to ensure flexibility into SoC. Matrix and hierarchical architectures are the two most popular architectures used to design an FPGA. This paper present firstly an embedded FPGA with hierarchical architecture, the configuration of this eFPGA is ensured by a loader with a proposed model. Then, we propose the first embedded FPGA having a matrix architecture with a multi-level switch box. With the best of our knowledge, this is the first work that presents a decoder which loads the bitstream words to eFPGA SRAMs cells for the mesh of cluster architectures. A series of experimentation is conducted to evaluate the proposed eFPGAs. The static power, latency, and hardware utilization, as well as hardware implementation, are discussed and analyzed. Mesh of cluster eFPGA introduces an area overhead ≈ 2 times of tree eFPGA size which is correlated to static power but has a straightforward benefit in terms of frequency and performance, regularity, and easy to implement.