Novel SRAM bias control circuits for a low power L1 data cache

Abstract

This paper proposes two novel bias control circuits to manage the power consumption of inactive cache cells in data retention mode. Both circuits have lower power consumption and area overheads when compared to previous proposals. The first proposed circuit (Dynamic Bias Control circuit or DB-Control circuit) dynamically tracks the reference current and sets the bias voltage of cells, while the second (Self-Adjust Bias Control circuit or SAB-Control circuit) has a self-adjust property to set the bias voltages and also alleviates the instability problems that appear due to noise injection. Although any SRAM array can benefit from these circuits, to show their usefulness, we frame our study on a recently proposed dual-versioning L1 data cache that has been designed for chip multi-processors that implement optimistic concurrency proposals, where leakage current has more effect on power dissipation and on circuit instability. Therefore, we add the proposed bias control circuits to a 32KB dual-versioning SRAM (dvSRAM) cache and simulate and optimize the entire cache with 45-nm CMOS technology at 2GHz processor frequency and 1V supply voltage. The simulations demonstrate the effectiveness of our proposed circuits to reduce the energy consumption of dvSRAM L1 data cache by 35.8% on average compared to the typical dvSRAM cache. This is achieved with a modest area increase of 1.6% per sub-array and negligible delay overhead. We also show that instability problems are alleviated by using the SAB-Control circuit.