Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture

Abstract

As FPGA densities have increased, the feasibility of using floatingpoint computations on FPGAs has improved. Moreover, recent innovations in FPGA architecture have changed the design tradeoff space by providing new fixed circuit functions which may be employed in floating-point computations. These include high density multiplier blocks and shift registers. This paper evaluates the use of such blocks for the design of a family of floating-point units including add/sub, multiplier, and divider. Portions of the units that would receive the greatest benefit from the use of multipliers and shift registers are identified. It is shown that the use of these results in significant area savings compared to similar floating-point units based solely on conventional LUT/FF logic. Finally, a complete floating-point application circuit that solves a classic heat transfer problem is presented.