Novel Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2D Inverse DWT

Abstract

This paper presents a novel memory efficient hardware architecture for 5/3 lifting-based two-dimensional (2D) inverse discrete wavelet transform (IDWT). The proposed architecture processes multiple levels of composition simultaneously using only one one-dimensional (1D) 5/3 lifting-based inverse vertical filter and only one 1D 5/3 lifting-based inverse horizontal filter. In case of [Formula: see text] levels of composition for [Formula: see text] image, the proposed 5/3 2D IDWT architecture requires the total memory of size less than [Formula: see text], which is lower memory size than memory size required in any other previously published architecture. In terms of total number of adders, total number of multipliers (shifters), total computing time and output latency, presented solution is comparable with other state-of-the-art solutions. Proposed hardware architecture is suitable for implementation in JPEG 2000 decoder, since default inverse filter for reversible transformation in JPEG 2000 standard is 5/3 IDWT filter.