Abstract
Notice of Violation of IEEE Publication Principles<br><br>"Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation"<br> by Xiaoxuan She, P.K. Samudrala<br> in the 2009 NASA/ESA Conference on Adaptive Hardware and Systems<br><br> After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.<br><br> This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and the coauthor (P.K. Samudrala) was added to the paper without his knowledge or permission.<br><br> Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:<br><br> "Selective Triple Modular Redundancy (STMR) for Single Event Upset (SEU) Tolerant for FPGAs"<br> by Praveen Kumar Samudrala Jeremy Ramos, and Srinivas Katkoori<br> in IEEE Transactions on Nuclear Science, Vol 51, No 5, October 2004, pp. 2957-2969<br><br> <br/> This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these sensitive gates. Selective TMR is tested against different circuits to prove its efficacy. With a small loss of SEU immunity, the proposed scheme can greatly reduce the area overhead as compare to TMR technique. Selective TMR scheme along with the readback and reconfiguration features of FPGAs can result into a very effective SEU mitigation technique.
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