Nonlinear current source charge scheme for comparator based switched capacitor integrator

Abstract

AbstractThe continuous development of complementary metal–oxide–semiconductor (CMOS) technology makes it difficult to design high speed and low power amplifiers. One of the appropriate alternatives is comparator‐based circuits. In this paper, a modified structure for comparator‐based switched‐capacitor integrator is presented. This structure increases the clock frequency considerably by using a nonlinear current source. The proposed integrator involves replacing the two linear current sources in conventional comparator‐based switched‐capacitor integrator with just one nonlinear current source. Also, the new logic part is presented, which reduces the circuit size and power dissipation consequently. The suggested circuit reduces integration dependency to the logic part while decreases charge transfer phases to just a single phase. According to the proposed structure, a first order comparator‐based switched‐capacitor integrator is designed in 0.18 μm complementary metal–oxide–semiconductor technology with a 100 MHz as the clock frequency.